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逻辑芯片
Part Number VCC (V) tpd max @; 3.3V (ns) I(OUT) mA Output Type Package Outlines Description
74AHC1G00 2~5.5 7.9 8 Push-Pull A. B 2 Input NAND Gate
74AHC1G02 2~5.5 7.9 8 Push-Pull A. B 2 Input  NOR Gate
74AHC1G04 2~5.5 7.1 8 Push-Pull A. B 1 Input   Inverter
74AHC1G08 2~5.5 8.8 8 Push-Pull A. B 2 Input  AND Gate
74AHC1G125/126 2~5.5 8 8 3 State A. B 2 Input 3-State Buffer OE Low/High
74AHC1G14 2~5.5 12.8 8 Push-Pull A. B 1 Input  Schmitt Trigger Inverter
74AHC1G32 2~5.5 7.9 8 Push-Pull A. B 2 Input OR Gate
74AHC1G86 2~5.5 11 8 Push-Pull A. B 2 Input XOR Gate
74AHC1GU04 2~5.5 7.1 8 Push-Pull A. B 1 Input Unbuffered Inverter
74AHCT1G00 4.5~5.5 8 Push-Pull A. B 2 Input NAND Gate
74AHCT1G02 4.5~5.5 8 Push-Pull A. B 2 Input NOR Gate
74AHCT1G04 4.5~5.5 8 Push-Pull A. B 1 Input Inverter
74AHCT1G08 4.5~5.5 8 Push-Pull A. B 2 Input AND Gate
74AHCT1G125/126 4.5~5.5 8 3 State A. B 2 Input 3-State Buffer OE Low/High
74AHCT1G14 4.5~5.5 8 Push-Pull A. B 1 Input Schmitt Trigger Inverter
74AHCT1G32 4.5~5.5 8 Push-Pull A. B 2 Input OR Gate
74AHCT1G86 4.5~5.5 8 Push-Pull A. B 2 Input XOR Gate
74LVC1G00 1.65~5.5 4.7 32 Push-Pull A.B.C.D.E 2 Input NAND Gate
74LVC1G02 1.65~5.5 4.5 32 Push-Pull A.B.C.D.E 2 Input NOR Gate
74LVC1G04/06 1.65~5.5 4.2 32 P-P/OP-D A.B.C.D.E 1 Input Single Inverter PP/OP-D
74LVC1G07 1.65~5.5 4.2 32 OP-D A.B.C.D.E 1 Input Single Buffer
74LVC1G08 1.65~5.5 4.5 32 Push-Pull A.B.C.D.E 2 Input AND Gate
74LVC1G10 1.65~5.5 5 32 Push-Pull D.F.F.G 3 Input NAND Gate
74LVC1G11 1.65~5.5 4.9 32 Push-Pull D.F.F.G 3 Input AND Gate
74LVC1G125/126 1.65~5.5 4.5 32 3 State A.B.C.D.E 3 State Buffer OE Low/High
74LVC1G14 1.65~5.5 4.6 32 Push-Pull A.B.D.E 1 Input Schmitt Trigger Inverter
74LVC1G17 1.65~5.5 5.5 32 Push-Pull A.B.D.E 1 Input Schmitt Trigger Buffer
74LVC1G32 1.65~5.5 4.5 32 Push-Pull A.B.C.D.E 2 Input OR Gate
74LVC1G57 1.65~5.5 6.3 32 Push-Pull D.F.F.G 3 Input Configurable Multi-Fucntion 
74LVC1G58 1.65~5.5 6.3 32 Push-Pull D.F.F.G 3 Input Configurable Multi-Functional 
74LVC1G86 1.65~5.5 5 32 Push-Pull A.B.C.D.E 2 Input XOR Gate
74LVC1G97 1.65~5.5 6.3 32 Push-Pull D.F.F.G 3 Input Configurable Multi-Functional 
74LVC1G98 1.65~5.5 6.3 32 Push-Pull D.F.F.G 3 Input Configurable Multi-Functional 
74LVCE1G00 1.4~5.5 4 32 Push-Pull A.B.E 2 Input NAND Gate
74LVCE1G02 1.4~5.5 4 32 Push-Pull A.B.E 2 Input NOR Gate
74LVCE1G04/06 1.4~5.5 3.8 32 P-P/OP-D A.B.E 1 Input Single Inverter PP/OP-D
74LVCE1G07 1.4~5.5 3.4 32 OP-D A.B.E 1 Input Single Buffer
74LVCE1G08 1.4~5.5 4 32 Push-Pull A.B.E 2 Input AND Gate
74LVCE1G125/126 1.4~5.5 4 32 3 State A.B.E 3 State Buffer OE Low/High
74LVCE1G32 1.4~5.5 4 32 Push-Pull A.B.E 2 Input OR Gate
74LVCE1G86 1.4~5.5 4.4 32 Push-Pull A.B.E 2 Input XOR Gate
74LVC2G04/06 1.65~5.5 4.1 32 P-P/OP-D D.E.F.G Dual 1 Input Inverter/OP-D
74LVC2G07 1.65~5.5 3.7 32 OP-D D.E.F.G Dual 1 input Buffer OP-D
74LVC2G14 1.65~5.5 6 32 Push-Pull D.E.F.G Dual 1 Input Schmitt Trigger Inverter
74LVC2G17 1.65~5.5 5.7 32 Push-Pull D.E.F.G Dual 1 Input Schmitt Trigger Buffer
74LVC2G34 1.65~5.5 4.1 32 Push-Pull D.E.F.G Dual 1 Input Buffer
74LVC00A 1.65~5.5 4.1 24 Push-Pull H Quad 2 Input NAND Gate
74LVC04A/06A 1.65~5.5 4.3 24 P-P/OP-D H HEX 1 Input Inverter/OP-D
74LVC07A 1.65~5.5 3.5 24 OP-D H HEX 1 Input Buffer
74LVC08A 1.65~5.5 3.9 24 Push-Pull H QUAD 2 Input AND Gate
74LVC125A/126A 1.65~5.5 4.6 24 3-State H QUAD 2 Input 3-State Buff OE Low/High
74LVC14A 1.65~5.5 4.3 24 Push-Pull H HEX 1 Input Schmitt Trigger Inverter
74LVC32A 1.65~5.5 3.6 24 Push-Pull H QUAD 2 Input OR Gate
74LVC86A 1.65~5.5 4.4 24 Push-Pull H QUAD 2 Input XOR Gate
封装表示: A:SOT25    B:SOT353    C:SOT553    D:DFN1010    E:DFN1410    F:SOT26    G:SOT363    H:TSSOP-14  

 

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